In 1998, Simplex company came up with a simple processor with a clock rate of 4.5 GHz and average CPI of 6. Later, they decided to upgrade the system by replacing simple processor with 5 stage pipelined processor. Due to internal pipeline delay, the processor clock is reduced to 2.5 GHz. Assume that the new system does not implement any techniques to avoid hazards. Find out the following.
a) Clock time in non pipeline processor
b) Execution time of non pipeline processor
c) Clock time in pipeline processor
d) Execution time of pipeline processor for 100 tasks
e) Speedup achieved in pipeline processor
Answer:
a) Clock time in non pipeline processor
Frequency of the clock = 4.5 GHz
Cycle time = 1 / frequency
= 1 / 4.5 GHz = 1 / 4.5 X 109 Hz
= 0.222 ns
b) Execution time of non pipeline processor
Non pipeline execution time to process one instruction
= No of clock cycles taken to execute one instruction
= 6 clock cycles
= 6 X 0.222 ns
= 1.333 ns
c) Clock time in pipeline processor
Frequency of the clock = 2.5 GHz
Cycle time = 1 / frequency
= 1 / 2.5 GHz
= 1 / 2.5 X 109 Hz
= 0.4 ns
d) Execution time of pipeline processor for 100 tasks
Ideally, one instruction is executed per clock cycle as there are no stalls in the pipeline. So,
Pipeline execution time = 1 clock cycle
= 0.4 ns
For 100 tasks = 100 X 0.4 = 40 ns
e) Speedup achieved in pipeline processor
Speed up = execution time by non pipeline / execution time by pipeline
= 1.333 / 0.4
= 3.33 ns