The supplementary memory system that temporarily stores frequently used instructions and data for quicker processing by CPU of a computer. Main memory consists of up to 2n addressable words, with each word having a unique n-bit address. there are M = 2n/K fixed length of blocks in main memory. where K - words The cache consists of m blocks called lines. The length of a line, not including tag and control bits, is the line size. As there are more blocks in main memory than lines in cache, an individual line cannot be uniquely and permanently dedicated to a particular block. Thus, each line includes a tag that identifies which particular block is currently being stored. The cache connects to the processor via data, control, and address lines. When a cache hit occurs, the data and address buffers are disabled and communication is only between processor and cache, with no system bus traffic. When a cache miss occurs, the desired address is loaded onto the system bus and the data are r...